The invention relates to chemical mechanical planarization (CMP) of semiconductor wafer materials and, more particularly, to CMP methods for polishing silica and silicon nitride from semiconductor wafers in shallow trench isolation (STI) processes.
Decreasing dimensions of devices and the increasing density of integration in microelectronic circuits have required a corresponding reduction in the size of isolation structures. This reduction places a premium on reproducible formation of structures that provide effective isolation, while occupying a minimum amount of the substrate surface.
The STI technique is a widely used semiconductor fabrication method for forming isolation structures to electrically isolate the various active components formed in integrated circuits. One major advantage of using the STI technique over the conventional LOCOS (Local Oxidation of Silicon) technique is the high scalability to CMOS (Complementary Metal-Oxide Semiconductor) IC devices for fabrication at the submicron level of integration. Another advantage is that the STI technique helps prevent the occurrence of the so-called bird's beak encroachment, which is characteristic to the LOCOS technique for forming isolation structures.
In the STI technique, the first step is the formation of a plurality of trenches at predefined locations in the substrate, usually by anisotropic etching. Next, silica is deposited into each of these trenches. The silica is then polished by CMP, down to the silicon nitride (stop layer) to form the STI structure. To achieve efficient polishing, the polishing slurry typically provides a high selectivity involving the removal rate of silica relative to silicon nitride (“selectivity”).
Unfortunately, highly selective slurries exhibit significant density dependence, causing die scale thickness variations. For example, as shown in FIGS. 1A-1D, a silicon substrate 1 is illustrated comprising a nitride layer 5 and an oxide layer 3. FIG. 1A illustrates the topography of the silicon substrate 1, pre-polishing, comprising “high” density regions 7 and “low” density regions 9. As the low density regions 9 are planarized, the high density regions 7 may still have a significant step height, as much as 3000 Å. Then, as the low density regions 9 are cleared, high density regions 7 may still have significant residual oxide 3, as much as 3000 Å. As a result, as the high density regions 7 are cleared, low density regions 9 may exhibit significant dishing, on the order of 500 Å or more.
Hattori et al., in EP 1479741A2, discloses a known method for polishing in STI processes. Although, the method of Hattori provides adequate selectivity, the ever-increasing density of integration in microelectronic circuits demand improved methods.
Hence, what is needed is a method for chemical-mechanical polishing of silicon dioxide (“silica”) and silicon nitride for shallow trench isolation processes having improved dishing.